Goal: Make sure the board won’t asplode when I plug it in.
I managed to not break the board after not working with it since last August. I did a careful check, made sure the wires weren’t plugged wrong, etc. After doing a bunch of checks, I plug it in, connect to the serial port, and it says ”▒▒▒▒▒ ▒▒▒▒▒!” instead of “Hello World!”
It turns out that one of the wires between the 6551 serial controller and the 6502 had come loose. But, because it was so close to working, even though the firmware was setting that bit of a register, it was almost working.
Goal: Get RAM hooked up and IO decoded
The 6502 is really nearly useless without some RAM, maybe about 256 bytes for the zero page and 256 bytes for the stack page. Otherwise, all you’ve got is three registers to work with.
Most of the modern designs tend towards a relatively friendly and easy memory mapper circuit. We started out just using an inverter on A15 to select between the ACIA and the RAM, but now we’ve got two devices and they are very different sizes, so the usual approach is to put an 8-input NAND gate on A14 down to A8 to get a control line for the IO.
What it turns out worked better for me was to just wire up the complete set of IO decoders right away to mimic the SBC-2 design as well as a later section of Dirk Grappendorf’s tutorial before trying to hook up the RAM, because the 3-to-8 decoder is adding an invert step.
The memory map here is pretty much:
- 0x0000-0x7EFF - The RAM
- 0x0000-0x00FF - Zero Page
- 0x0100-0x01FF - Stack page
- 0x0200-0x7EFF - Available memory
- 0x7F00-0x7FFF - IO, where the first few bytes are the ACIA
- 0x8000-0xFFFF - The first 32k of the flash ROM
The whole works is getting way too unreliable at this point. Every time I add wires, I have to figure out what came loose.
I think the next step is to design a PCB because then I don’t need to solder a bunch of 8-bit buses across a perfboard.